Abstract—The corrosion behavior of Zr-based amorphous alloys investigated at high temperature in aqueous nitric acid environment. Weight loss studies have been performed to determine the corrosion resistance of Zr59Nb3Al10Ni8Cu20 and Zr60Pd5Al10Ni10Cu15 amorphous alloys in aqueous HNO3 media at boiling temperature. The SEM micrographs have been obtained to know the surface morphology of specimens after immersion in aqueous HNO3 media. These results revealed the fact that Zr60Pd5Al10Ni10Cu15 amorphous alloys showed poor corrosion resistance than Zr59Nb3Al10Ni8Cu20 in aqueous HNO3 media at boiling temperature.

Abstract— There has been a phenomenal growth in e-commerce in last few years and it still growing. The most successful and experienced companies related to E-Commerce realize that key determinant of success and failure of any website are not merely a web presence or low price but the delivery on high quality websites along with its security. A framework and model is required to attain the desired quality of website. Evaluation criteria include design, security, usability and performance for websites etc. This paper provides a review based on different authors to establish Quality. The main goal are identifying factors through different research papers and categorizing these factors.

Abstract— Flip-flops are the major storage elements in all SOC’s of digital design.They accommodate most of a power that has been applied to the chip. Flip-flop is one of a most power consumption component.It is important to reduce a power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to clock delays. The delay of a flip-flops should be minimized for efficient implementation. The concept of this project is to reduce the power consumption and to increase the speed and functionality of the chip. This project moves around in replacing conventional master-slave based flip flop to a pulse triggered flip flop which acts as a tribute alternate for low power applications. Initially in the critical path the pulse generation controls logic along with SVL function. A simple transistor SVL design is used to reduce the circuit complexity. In this scheme transistor sizes and pulse generation circuit can be further reduce for power saving. Here UMC CMOS180nm technology is use in SPICE tool to design the proposed structure. This would bring up the result in power saving approximately to 38.4%.

Abstract— This paper presents a design of double layer microstrip patch antenna and experimentally studied on IE3D, an electromagnetic simulation package by Zeland Software Inc.. Double layers microstip patch antenna is designed on a FR4 substrate of thickness 1.524 mm and relative permittivity of 4.4 and mounted above the ground plane at a height of 1.6 mm. Bandwidth as high as 8.1 % are achieved with stable pattern characteristics, such as gain and cross polarization, within its bandwidth. Impedance bandwidth, antenna gain and return loss are observed for the proposed antenna. Details of the measured and simulated results are presented and discussed.

Abstract— This paper presents a direct design of Infinite Impulse Response filters (IIR filters) which minimizes group delay without changing the magnitude response of filters. In this paper Butterworth and Chebyshev1 lowpass filters are designed by using allpass filters. The design specifications are passband and stopband frequencies and passband ripple and stopband attenuation.